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| VDD VIN+ T/H VIN- VREF 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK AD7452 SDATA CONTROL LOGIC CS GND t1 CS t2 SCLK 1 2 3 4 t5 5 tCONVERT B 13 14 15 16 t3 SDATA 0 0 0 4 LEADING ZEROS t4 0 DB11 t7 DB10 DB2 t6 DB1 t8 DB0 tQUIET THREE-STATE 1.6mA IOL TO OUTPUT PIN 1.6V CL 25pF 200 A IOH VDD 1 SCLK 2 SDATA 3 8 VREF VIN+ TOP VIEW 6 VIN- (Not to Scale) CS 4 5 GND 7 AD7452 75 VDD = 5.25V VDD = 4.75V 0 -20 8192 POINT FFT fSAMPLE = 555kSPS fIN = 100kSPS SINAD = 71.7dB THD = -82dB SFDR = -83dB 70 VDD = 3.6V SINAD (dB) VDD = 2.7V 65 -40 -60 -80 60 03154-A-005 -100 -120 -140 0 100 200 FREQUENCY (kHz) 277 55 10 FREQUENCY (kHz) 100 277 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 VDD = 5V 100 1000 FREQUENCY (kHz) 10000 VDD = 3V 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4096 0 100mV p-p SINE WAVE ON VDD NO DECOUPLING ON VDD 1.0 0.8 0.6 0.4 0.2 -20 -40 -60 0 VDD= 3V -0.2 VDD= 5V -0.4 -0.6 -0.8 -80 -100 -120 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY (kHz) 900 1000 -1.0 0 1024 2048 CODE 3072 4096 3.0 2.5 2.0 1.5 2.0 1.5 1.0 0.5 POSITIVE INL 1.0 POSITIVE DNL 0.5 0 -0.5 -1.0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 -0.5 -1.5 NEGATIVE DNL -2.0 0 0.5 1.0 VREF (V) 1.5 2.0 2.2 2.5 NEGATIVE INL 0 2.5 2.0 8 7 6 5 VDD = 5V 1.5 1.0 POSITIVE DNL 0.5 4 3 0 -0.5 -1.0 0 0.5 1.0 VREF (V) 1.5 2.0 2.2 2.5 2 NEGATIVE DNL 1 0 0 VDD = 3V 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 NEGATIVE INL POSITIVE INL 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 VDD = 3V VDD = 5V 10,000 9,000 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,000 VIN+ = VIN- 10,000 CONVERSIONS fS = 555kSPS 10,000 CODES 0 2044 2045 2046 CODE 2047 2048 2049 CAPACITIVE DAC B VIN+ A A B VREF CS SW1 SW3 VIN- SW2 CS COMPARATOR CAPACITIVE DAC CONTROL LOGIC 1LSB = 2 011...111 011...110 CAPACITIVE DAC B VIN+ A A B CS SW1 SW3 VIN- SW2 VREF CS COMPARATOR CAPACITIVE DAC CONTROL LOGIC 100...010 100...001 100...000 -VREF 1LSB 000...001 000...000 111...111 VREF/4096 + VREF - 1LSB 0 LSB ANALOG INPUT (VIN+ -VIN-) 0.1 F 10 F 3V/5V SUPPLY SERIAL INTERFACE VDD VREF p-p VREF p-p CM* VIN+ SCLK AD7452 CM* VIN- VREF SDATA CS C/ P 4.5 4.0 GND 3.5 2V/2.5V VREF 0.1 F 3.25V 3.0 2.5 2.0 COMMON-MODE RANGE *CM IS THE COMMON-MODE VOLTAGE. 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 1.75V 3.5 2.5 2V 2.0 VREF p-p VIN+ AD7452 COMMONMODE VOLTAGE VREF p-p VIN- 1.5 COMMON-MODE RANGE 1.0 1V 0.5 0 0 0.25 0.50 0.75 1.00 1.25 VREF (V) 1.50 1.75 2.00 REFERENCE = 2V VIN- COMMON-MODE (CM) CMMIN = 1V CM MAX = 4V 2V p-p VIN+ REFERENCE = 2.5V VIN- COMMON-MODE (CM) CM MIN = 1.25V CMMAX = 3.75V 2.5V p-p VIN+ 0 TA = 25C VDD = 5V -20 -40 RIN = 1k RIN = 510 -60 -80 RIN = 300 277 -100 10 RIN = 10 100 INPUT FREQUENCY (kHz) VDD D VIN+ C1 D R1 C2 -50 TA = 25C -55 VDD -60 -65 R1 C1 D -75 VDD = 3.6V -80 -85 -90 10 VDD = 4.75V 100 INPUT FREQUENCY (kHz) VDD = 5.25V 277 VDD = 2.7V C2 -70 D VIN- RF1 RG1 +2.5V GND -2.5V VOCM 51 RG2 RS* 3.75V 2.5V 1.25V VIN+ AD8138 RS* C* AD7452 VIN- C* 3.75V 2.5V 1.25V VREF RF2 *MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED. RS-50 ; C-1nF RG1 = RF1 = RF2 = 499 ; RG2 = 523 EXTERNAL VREF (2.5V) 220 2 VREF GND V- 220 220 V+ 27 V- 10k EXTERNAL VREF 0.1 F VIN- VIN+ VREF p-p 390 V+ 27 VDD AD7452 VREF A 220 2 GND VREF p-p 390 V+ 27 V- 220 220 220 V+ A V- 10k EXTERNAL VREF VIN- VIN+ VDD 3.75V 2.5V 1.25V R R VIN+ AD7452 R VREF C AD7452 VIN- 3.75V 2.5V 1.25V VREF 27 0.1 F 20k EXTERNAL VREF (2.5 V) VDD AD780 NC VDD 1 2 3 AD7452* NC NC 2.5V NC 0.1 F VREF OPSEL 8 VIN 7 TEMP VOUT 6 GND TRIM 5 0.1 F 10nF 0.1 F 4 NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY R +2.5V 0V -2.5V R VIN R R 5V 2.5V 0V VIN+ AD7452 0.1 F VIN- VREF EXTERNAL VREF (2.5V) CS 10ns t2 SCLK 1 2 3 4 t5 5 tCONVERT 13 14 15 16 t6 t8 tQUIET tACQUISITION 12.5(1/FSCLK) 1/THROUGHPUT CS 12 10 SCLK SDATA THREE-STATE CS 1 SCLK 10 16 SDATA 4 LEADING ZEROS + CONVERSION RESULT tPOWER-UP CS A SCLK 1 PART BEGINS TO POWER UP THIS PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED 10 16 1 10 16 SDATA INVALID DATA VALID DATA 100 10 VDD = 5V 1 VDD = 3V 0.1 0.01 0 50 100 150 200 250 THROUGHPUT (kSPS) 300 350 AD7452* ADSP-21xx* AD7452* SCLK TMS320C5x/ C54x* CLKx CLKR SCLK SDATA CS SCLK DR RFS TFS SDATA CS DR FSx FSR *ADDITIONAL PINS REMOVED FOR CLARITY *ADDITIONAL PINS REMOVED FOR CLARITY AD7452* DSP56xxx* SCLK SDATA CS SCLK SRD SR2 *ADDITIONAL PINS REMOVED FOR CLARITY 2.90 BSC 8 7 6 5 1.60 BSC 1 2 3 4 2.80 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.38 0.22 0.22 0.08 8 4 0 0.15 MAX SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178BA |
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